A digital PLL device as shown in FIG. 10 is conventionally used for certainly obtaining a clock signal with high reliability over a digital synchronous network. The conventional digital PLL device comprises selector 1, phase comparator 2, digital voltage control oscillator (D-VCO) 5, loop filter 6, and controller 7.
In a digital PBX, for example, a digital PLL device for generating a timing signal is installed in a main card as a primary master and the other input/output (I/O) (secondary master) cards. This digital PLL device receives first synchronous timing signal “a” from the primary master, and receives second synchronous timing signal “b” from the other I/O card when it cannot normally receive first synchronous timing signal “a”. Selector 1 selects any synchronous timing signal and sends it as synchronous timing signal “d” to phase comparator 2.
Phase comparator 2 compares a phase of synchronous timing signal “d” with that of internal timing signal “c” generated by dividing a clock signal created by the D-VCO with a loop filter. Phase comparator 2 sends a signal corresponding to the phase difference, namely phase correction signal “e”, to D-VCO 5. D-VCO 5 generates a clock signal with a frequency corresponding to the phase difference. Specifically, D-VCO 5 decreases the frequency when the phase of the internal timing signal has advanced, and increases the frequency when the phase has delayed. Loop filter 6 divides the clock signal sent from D-VCO 5 by N, and outputs an internal timing signal.
Phase comparator 2, D-VCO 5, and loop filter 6 configure a digital PLL circuit.
Each I/O card normally creates clock signal “f” at the loop filter 6. Clock signal “f” synchronizes with first synchronous timing signal “a” transmitted from the main card (primary master). Clock signal “f” is supplied to a required circuit in the device through an output terminal.
When first synchronous timing signal “a” to be received is interrupted, controller 7 detects the interruption of first synchronous timing signal “a”, and switches the signal to second synchronous timing signal “b”. Until first synchronous timing signal “a” is recovered, clock signal “f” synchronizing with second synchronous timing signal “b” is created.
When conventional digital PLL device changes over the first synchronous timing signal to the second synchronous timing signal for protecting against fault occurrence in the first synchronous timing signal, synchronous timing signal “d” to be fed into phase comparator 2 momentarily interrupts. The momentary interruption causes frequency fluctuation of clock signal “f”.